Visible to Intel only — GUID: pze1494232365965
Ixiasoft
1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
Visible to Intel only — GUID: pze1494232365965
Ixiasoft
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
The Mailbox Client Intel FPGA IP is an Avalon® memory-mapped interface slave component that must connect to an Avalon® memory-mapped interface master. The simplest Avalon® memory-mapped interface master is the JTAG-to-Avalon Master.
The rsu1.tcl script provides examples to perform all the available command functions. You can run the functions available in the rsu1.tcl script via System Console of the Quartus® Prime software.
The following example shows how to access the quad SPI flash memory. Follow this sequence to prevent errors.
- QSPI_OPEN
- QSPI_SET_CS
- Any of the following quad SPI operations:
- QSPI_READ
- QSPI_WRITE
- QSPI_ERASE
- QSPI_READ_DEVICE_REG
- QSPI_WRITE_DEVICE_REG
- QSPI_SEND_DEVICE_OP
- QSPI_CLOSE