Visible to Intel only — GUID: lum1707961656664
Ixiasoft
1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
Visible to Intel only — GUID: lum1707961656664
Ixiasoft
1.1. Release Information
Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
The IPs listed in this section are referred to collectively as Mailbox Client Intel® FPGA IP throughout this document unless otherwise noted.
Item | Description |
---|---|
IP Version | 22.0.0 |
Quartus® Prime Pro Edition Version | 24.2 |
Release Date | 2024.07.08 |
Item | Description |
---|---|
IP Version | 1.0.0 |
Quartus® Prime Pro Edition Version | 24.2 |
Release Date | 2024.07.08 |