Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4. Mailbox Client Intel® FPGA IP Core Interface Signals

The host communicates with the Mailbox Client Intel® FPGA IP over its Avalon® memory-mapped interface.

Through the AXI manager interface, the crypto service has access to the lowest 1GB of memory, with a maximum data size of 512 MB per each read and write operation.

Note: For Agilex™ 7 and Agilex™ 5 devices, the AXI manager interface is available if you enabled the Enable Crypto Service parameter.
The following figure illustrates the Mailbox Client Intel® FPGA IP interfaces.
Figure 2.  Mailbox Client Intel® FPGA IP InterfacesThe AXI manager interface is only available in the Agilex™ 7 and Agilex™ 5 devices with the Enable Crypto Service parameter enabled.
Note: For information about the AXI manager interface, refer to the AXI Manager Interface table.
Note: The avmm_waitrequest signal is mandatory in Quartus® Prime software version 23.2 or later.

Section Content
Clock and Reset Interfaces
Avalon Memory-Mapped Interface
AXI Manager Interface

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