Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II HAL Driver x
1.10.1. Driver API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.3.3. AXI Manager Interface

The AXI manager interface is standard advanced extensible interface (AXI). This interface is accessible when you enabled the crypto services features. The crypto services features are available for the Intel® Agilex™ devices.
Table 4.  AXI Manager InterfaceThe table displays command, response, and urgent interface signals.
Signal Role Width Direction Description
AXI Manager Clock and Reset Signals
axi_in_clk 1 Input

AXI* interface clock.

axi_in_reset 1 Input

AXI* interface reset.

AXI Manager Write Address Channel Signals
axi_target_awid 4 Output AXI* identification tag for write transaction.
axi_target_awaddr 32 Output AXI* address of the first transfer in a write transaction.
axi_target_awlen 8 Output AXI* length. Identifies the exact number of data transfers in a write transaction.
axi_target_awsize 3 Output

AXI* size. Identifies the number of bytes in each data transfer in a write transaction.

axi_target_awburst 2 Output

AXI* burst type. Indicates how address changes between each transfer in a write transaction.

axi_target_awlock 1 Output

Provides information about the atomic characteristics of a AXI* write transaction.

axi_target_awcache 4 Output Indicates how a write transaction is required to progress through a system.
axi_target_awprot 3 Output

Protection attributes of a write transaction: privilege, security level, and access type.

axi_target_awqos 4 Output

Quality of Service identifier for a write transaction

axi_target_awvalid 1 Output

AXI* valid signal for a write transaction.

Indicates that the write address channel signals are valid.

axi_target_awuser 5 Output User-defined extension for the write address channel.
axi_target_awready 1 Input

AXI* ready signal for write address.

Indicates that a transfer on the write address channel can be accepted.

AXI Manager Write Data Channel Signals
axi_target_wdata 64 Output

AXI* write data.

axi_target_wlast 1 Output

AXI* write transaction last data transfer. Indicates whether the current transfer is the last data transfer in a write transaction.

axi_target_wready 1 Input

AXI* ready signal for write data. Indicates that a write data channel transfer can be accepted.

axi_target_wvalid 1 Output

AXI* valid signal for write data. Indicates that a write data channel signals are valid.

axi_target_wstrb 8 Output

AXI* write strobes. Indicates the byte lane holding valid data.

AXI Manager Write Response Channel Signals
axi_target_bid 4 Input AXI* identification tag for write response.
axi_target_bresp 2 Input

AXI* write response. Indicates write response status.

axi_target_bvalid 1 Input

AXI* valid signal for write response. Indicates that the write response channel signals are valid.

axi_target_bready 1 Output

AXI* ready signal for write response. Indicates that the write response channel transfer can be accepted.

AXI Manager Read Data Channel Signals
axi_target_rdata 64 Input

AXI* read data.

axi_target_rresp 2 Input

AXI* read response. Indicates read transfer status.

axi_target_rlast 1 Input

AXI* read transaction last data transfer. Indicates whether the current transfer is the last data transfer in a read transaction.

axi_target_rready 1 Output

AXI* read data channel ready signal. Indicates that a transfer on the read data channel can be accepted.

axi_target_rvalid 1 Input

AXI* valid signal for read data channel. Indicates that the read data channel signals are valid.

axi_target_rid 4 Input AXI* identification tag for read data and response.
AXI Manager Read Response Channel Signals
axi_target_arid 4 Output

AXI* identification tag for read address transaction.

axi_target_araddr 32 Output

AXI* address of the first transfer in a read transaction.

axi_target_arlen 8 Output

AXI* length. Identifies the number of data transfers during the read transaction.

axi_target_arsize 3 Output AXI* size.

Identifies the number of bytes in each data transfer in a read transaction.

axi_target_arburst 2 Output

AXI* burst type. Indicates how address changes between each transfer in a read transaction.

axi_target_arlock 1 Output Provides information about the atomic characteristics of a AXI* read transaction.
axi_target_arcache 4 Output Indicates how a read transaction is required to progress through a system.
axi_target_arprot 3 Output

Protection attributes of a read transaction: privilege, security level, and access type.

axi_target_arqos 4 Output Quality of Service identifier for a read transaction.
axi_target_arvalid 1 Output

AXI* valid signal for read transaction. Indicates that the read address channel signals are valid.

axi_target_aruser 5 Output AXI* user-defined extension for the read address channel.
axi_target_arready 1 Input

AXI* read address channel ready signal. Indicates that a transfer on the read address channel can be accepted.

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