Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 4/04/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II HAL Driver x
1.10.1. Driver API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map

Table 5.   Avalon® MM Memory Map
Offset (word) R/W 31 30:2 1 0
Base address + 0 W Command
Base address + 1 W Command last word (eop)
Base address + 2 R Command FIFO empty space
Base address + 3 N/A Reserved
Base address + 4 N/A Reserved
Base address + 5 R Response data
Base address + 6 R Response FIFO fill level EOP SOP
Base address + 7 R/W Interrupt enable register (IER)
Base address + 8 R Interrupt status register (ISR)
Base address + 9 R/W Timer 1 enable Timer 1 period
Base address + 10 R/W Timer 2 enable Timer 2 period
Level Two Title