Mailbox Client Intel® FPGA IP User Guide

ID 683290
Date 4/04/2022
Public

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1.3.2. Avalon® Memory-Mapped Interface

The Avalon® MM interface is standard memory-mapped interface. For detailed definitions of these signals, refer to the Avalon® Memory-Mapped Interfaces chapter in the Avalon Interface Specifications.

Table 3.   Avalon® Memory-Mapped Interface
Signal Role Width Direction Description
avmm_address 4 Input Avalon® MM address.
avmm_write 1 Input Avalon® MM write request.
avmm_read 1 Input Avalon® MM read request.
avmm_writedata 32 Input Avalon® MM write data bus.
avmm_readdata 32 Output Avalon® MM read data bus.
avmm_readdatavalid 1 Output Avalon® MM read data valid.