Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II HAL Driver x
1.10.1. Driver API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1. Mailbox Client Intel FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 20.1.2

The Mailbox Client Intel FPGA IP is a bridge between a host and the secure device manager (SDM). Available for Intel® Stratix® 10 and Intel® Agilex™ devices, you use the Mailbox Client Intel FPGA IP to send commands and receive status from SDM peripheral clients. The Mailbox Client defines functions that the SDM runs.

The following pre-defined functions are available:
  • Reading the Chip ID
  • Reading temperature sensors
  • Reading voltage sensors
  • Reading and writing external quad serial peripheral interface (SPI) flash memory
  • Performing remote system updates (RSU)
  • Enabling cryptographic services 1

The following block diagram shows how to use the Mailbox Client Intel FPGA IP in an interactive session. The diagram also emphasizes different ways of communicating with IP through the Host Controller.

Figure 1. Mailbox Client Intel FPGA IP System Block Diagram
This block diagram includes the following components:
  • Host Controller: provides possible ways of accessing the Mailbox Client Intel FPGA IP. Use any of the specified ways to communicate with the host controller:
    • System Console with the JTAG to Avalon® Master Bridge Intel FPGA IP. The System Console provides a Tcl Console pane that you can use to run the IP functions. The JTAG to Avalon® Master Bridge Intel FPGA IP translates the commands it receives from the System Console to Avalon® Memory-Mapped ( Avalon® MM) format that the Mailbox Client Intel FPGA IP requires.
    • Nios® II processor: sends commands to the Mailbox Client Intel FPGA IP.
    • Custom logic: It sends commands to the Mailbox Client Intel FPGA IP.
    • PCIe* Hard IP
    • Ethernet IP

  • Mailbox Client Intel FPGA IP: drives commands and receives responses from the SDM. This component includes FIFOs with a maximum depth of 1024 entries to store commands and responses. The Mailbox Client Intel FPGA IP interrupt indicates when the input FIFO in full and when the output FIFO contains valid data. You can size these FIFOs to accommodate the commands the you intend to send.

Intel provides a reference design that uses the System Console and the JTAG master to drive the Mailbox Client Intel FPGA IP. In the Intel Design Store, search for Intel® Agilex™ Mailbox Client Intel® FPGA IP Core Design Example (QSPI flash Access and Remote System Update) to view the design.

Related Information
1 This feature is available for Intel® Agilex™ devices in Intel® Quartus® Prime software version 21.3 or later.
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