Mailbox Client Intel® FPGA IP User Guide

Download PDF
ID 683290
Date 11/10/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Target Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II HAL Driver x
1.10.1. Driver API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.2. Parameters

Parameter Name Value Description
Mailbox Client Parameters
Command FIFO Depth 1 - 1024 Depth of the command FIFO
Response FIFO Depth 1 - 1024 Depth of the response FIFO
Crypto Memory Timeout Value 0x00002710

-

0x7FFFFFFFF

 The timeout for the cryptographic service. Specify value within the minimum and maximum timeout value.
  • 0x7FFFFFFF: Maximum memory timeout value
  • 0x002710: Minimum memory timeout value
Memory Target Parameters
HAS_OFFLOAD 2

0, 1

 Enables the cryptographic offloading feature. When set, enables the crypto AXI target interface.
2 This feature is only available for Intel® Agilex™ devices.
Level Two Title