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1.1. Device Family Support
1.2. Parameters
1.3. Mailbox Client Intel FPGA Core Interface Signals
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map
1.5. Commands and Responses
1.6. Specifying the Command and Response FIFO Depths
1.7. Enabling Cryptographic Services
1.8. Using the Mailbox Client Intel FPGA IP
1.9. Mailbox Client Intel FPGA IP Core Use Case Examples
1.10. Nios® II HAL Driver
1.11. Mailbox Client Intel FPGA IP User Guide Archives
1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
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1.9. Mailbox Client Intel FPGA IP Core Use Case Examples
The Mailbox Client Intel FPGA IP is an Avalon® MM slave component that must connect to an Avalon® MM master. The simplest Avalon® MM master is the JTAG-to-Avalon Master.
The rsu1.tcl script provides examples to perform all the available command functions. You can run the functions available in the rsu1.tcl script via System Console of the Intel® Quartus® Prime software.
The following example shows how to access the quad SPI flash memory. Follow this sequence to prevent errors. Refer to for more information about these commands.
- QSPI_OPEN
- QSPI_SET_CS
- Any of the following quad SPI operations:
- QSPI_READ
- QSPI_WRITE
- QSPI_ERASE
- QSPI_READ_DEVICE_REG
- QSPI_WRITE_DEVICE_REG
- QSPI_SEND_DEVICE_OP
- QSPI_CLOSE
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