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1.1. Device Family Support
1.2. Parameters
1.3. Mailbox Client Intel FPGA Core Interface Signals
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map
1.5. Commands and Responses
1.6. Specifying the Command and Response FIFO Depths
1.7. Enabling Cryptographic Services
1.8. Using the Mailbox Client Intel FPGA IP
1.9. Mailbox Client Intel FPGA IP Core Use Case Examples
1.10. Nios® II HAL Driver
1.11. Mailbox Client Intel FPGA IP User Guide Archives
1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
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1.3.2. Avalon® Memory-Mapped Interface
The Avalon® MM interface is standard memory-mapped interface. For detailed definitions of these signals, refer to the Avalon® Memory-Mapped Interfaces chapter in the Avalon Interface Specifications.
Signal Role | Width | Direction | Description |
---|---|---|---|
avmm_address | 4 | Input | Avalon® MM address. |
avmm_write | 1 | Input | Avalon® MM write request. |
avmm_read | 1 | Input | Avalon® MM read request. |
avmm_writedata | 32 | Input | Avalon® MM write data bus. |
avmm_readdata | 32 | Output | Avalon® MM read data bus. |
avmm_readdatavalid | 1 | Output | Avalon® MM read data valid. |