Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 11/10/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel FPGA Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
1.3. Mailbox Client Intel FPGA Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Target Interface
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II HAL Driver x
1.10.1. Driver API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.1. Device Family Support

The following lists the device support level definitions for Intel FPGA IPs:
  • Advance support — The IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
  • Preliminary support — The IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
  • Final support — The IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs.
Table 1.  Device Family Support
Device Family Support
Intel® Stratix® 10 Final
Intel® Agilex™ Final
Related Information
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