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1.1. Device Family Support
1.2. Parameters
1.3. Mailbox Client Intel FPGA Core Interface Signals
1.4. Mailbox Client Intel FPGA IP Avalon® MM Memory Map
1.5. Commands and Responses
1.6. Specifying the Command and Response FIFO Depths
1.7. Enabling Cryptographic Services
1.8. Using the Mailbox Client Intel FPGA IP
1.9. Mailbox Client Intel FPGA IP Core Use Case Examples
1.10. Nios® II HAL Driver
1.11. Mailbox Client Intel FPGA IP User Guide Archives
1.12. Document Revision History for the Mailbox Client Intel FPGA IP User Guide
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1.5. Commands and Responses
The host controller communicates with the SDM using command and response packets via the Mailbox Client Intel® FPGA IP.
The first word of the command and response packets is a header that provides basic information about the command or response.
Figure 3. Command and Response Header Format
The following table describes the fields of the header command.
Header | Bit | Description |
---|---|---|
Reserved | [31:28] | Reserved. |
ID | [27:24] | The command ID. The response header returns the ID specified in the command header. Refer to Operation Commands for command descriptions. |
0 | [23] | Reserved. |
LENGTH | [22:12] | Number of words of arguments following the header. The IP responds with an error if a wrong number of words of arguments is entered for a given command. |
Reserved | [11] | Reserved. Must be set to 0. |
Command Code/Error Code | [10:0] | Command Code specifies the command. The Error Code indicates whether the command succeeded or failed. In the command header, these bits represent command code. In the response header, these bits represent error code. If the command succeeds, the Error Code is 0. If the command fails, refer to the error codes defined in the Error Code Responses. |