F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. Reconfiguration Interfaces
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
5.10. Reconfiguration Interfaces x
5.10.1. CPRI PHY Reconfiguration Interface 5.10.2. Ethernet Reconfiguration Interface 5.10.3. Transceiver Reconfiguration Interface
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

5.6. TX Interface (8b/10b)

The TX 8b/10b interface is available only when you select the Enable reconfiguration to 8b/10b datapath parameter or when you select the 8b/10b CPRI line rate. For the CPRI PHY core power up in 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter 8b/10b line rate.

Table 20.  TX 8b/10b Interface
Port Name Width (Bits) Domain Description
i_tx_d[15:0] 16 o_tx_clkout2 Indicates 8b/10b TX data for the corresponding CPRI PHY channel.
i_tx_c[1:0] 2 o_tx_clkout2 Indicates 8b/10b TX control for the corresponding CPRI PHY channel.
When you transmit the data using the TX 8b/10b interface:
  • The frames are 8b/10b encoded.
    • Each byte in i_tx_d has a corresponding bit in i_tx_c that indicates whether the byte is a control byte or a data byte. For example, i_tx_c[1] is the control bit for i_tx_d[15:8].
  • The byte order for the TX interface flows from right to left and the first byte that the core transmits is i_tx_d[7:0].
  • The first bit that the core transmits is i_tx_d[0].
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