F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. Reconfiguration Interfaces
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
5.10. Reconfiguration Interfaces x
5.10.1. CPRI PHY Reconfiguration Interface 5.10.2. Ethernet Reconfiguration Interface 5.10.3. Transceiver Reconfiguration Interface
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

1.5. Resource Utilization

The resources for the F-Tile CPRI PHY Intel® FPGA IP core are obtained from the Intel® Quartus® Prime Pro Edition software version 21.3.

Table 4.  Resource Utilization for Intel® Agilex™ Devices
CPRI Line Bit Rate (With number of channel1) ALMs ALUTs Dedicated Logic Registers Memory 20K
24.33024 Gbps with RS-FEC 4786 6071 7724 13
24 Gbps without RS-FEC 4760 6069 7739 13
12.1651 Gbps with RS-FEC 4775 6069 7733 13
12.1651 Gbps without RS-FEC 4776 6069 7739 13
10.1376 Gbps with RS-FEC 4771 6069 7738 13
10.1376 Gbps without RS-FEC 4771 6069 7738 13
9.8304 Gbps 5179 6689 8911 13
6.144 Gbps 5179 6691 8885 13
4.9152 Gbps 5181 6694 8871 13
3.072 Gbps 5179 6691 8897 13
2.4576 Gbps 5188 6694 8892 13
1.2288 Gbps 5192 6694 8890 13
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