F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 10/04/2021
Public

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Document Table of Contents

5.10.1. CPRI PHY Reconfiguration Interface

Table 24.  CPRI PHY Reconfiguration Interface
Port Name Width (Bits) Domain Description
i_reconfig_cpri_addr[3:0] 4 i_reconfig_clk Address for F-tile CPRI PHY CSRs in selected channel. Using word addressing format.
i_reconfig_cpri_read 1 i_reconfig_clk Read command for F-tile CPRI PHY CSRs in selected channel.
i_reconfig_cpri_write 1 i_reconfig_clk Write command for F-tile CPRI PHY CSRs in selected channel.
o_reconfig_cpri_readdata[31:0] 32 i_reconfig_clk Read data from reads to F-tile CPRI PHY CSRs in selected channel.
o_reconfig_cpri_readdatavalid 1 i_reconfig_clk Read data from F-tile CPRI PHY CSRs is valid in selected channel.
i_reconfig_cpri_writedata[31:0] 32 i_reconfig_clk Data for writes to F-tile CPRI PHY CSRs in selected channel.
o_reconfig_cpri_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on F-tile CPRI PHY CSRs in selected channel.
Figure 10. Writing to CPRI PHY Reconfiguration
Figure 11. Reading from CPRI PHY Reconfiguration