F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 10/04/2021
Public

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4.2.2. Calculation for 64b/66b Datapath

If the 64b/66b datapath RSFEC is enabled, execute the following steps to configure the DL logic in F-tile before RX latency calculation:
  1. Ensure the o_rx_blocklock signal is asserted.
  2. Read the RSFEC code word position value from e25g_stat_s0_rsfec_cw_pos_rx register, num field via Ethernet reconfiguration interface.
  3. Program the RSFEC code word position value to FGT ux_q_dl_ctrl_a_l<x> register, cfg_rx_lat_bit_for_async field via Transceiver reconfiguration interface. The ux_q_dl_ctrl_a_l<x> register is based on the placement of the FGT transceiver.
    1. FGT15, FGT11, FGT7, FGT3: ux_q_dl_ctrl_a_l3
    2. FGT14, FGT10, FGT6, FGT2: ux_q_dl_ctrl_a_l2
    3. FGT13, FGT9, FGT5, FGT1: ux_q_dl_ctrl_a_l1
    4. FGT12, FGT8, FGT4, FGT0: ux_q_dl_ctrl_a_l0
  4. Reset the deterministic measure logic for RX datapath by asserting rx_dl_restart bit at register offset 0x8 via reconfig_cpri interface.
  5. Release the reset for deterministic measure logic for RX datapath by clearing rx_dl_restart bit at register offset 0x8 via reconfig_cpri interface.