F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. Reconfiguration Interfaces
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
5.10. Reconfiguration Interfaces x
5.10.1. CPRI PHY Reconfiguration Interface 5.10.2. Ethernet Reconfiguration Interface 5.10.3. Transceiver Reconfiguration Interface
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

4.2.2. Calculation for 64b/66b Datapath

If the 64b/66b datapath RSFEC is enabled, execute the following steps to configure the DL logic in F-tile before RX latency calculation:
  1. Ensure the o_rx_blocklock signal is asserted.
  2. Read the RSFEC code word position value from e25g_stat_s0_rsfec_cw_pos_rx register, num field via Ethernet reconfiguration interface.
  3. Program the RSFEC code word position value to FGT ux_q_dl_ctrl_a_l<x> register, cfg_rx_lat_bit_for_async field via Transceiver reconfiguration interface. The ux_q_dl_ctrl_a_l<x> register is based on the placement of the FGT transceiver.
    1. FGT15, FGT11, FGT7, FGT3: ux_q_dl_ctrl_a_l3
    2. FGT14, FGT10, FGT6, FGT2: ux_q_dl_ctrl_a_l2
    3. FGT13, FGT9, FGT5, FGT1: ux_q_dl_ctrl_a_l1
    4. FGT12, FGT8, FGT4, FGT0: ux_q_dl_ctrl_a_l0
  4. Reset the deterministic measure logic for RX datapath by asserting rx_dl_restart bit at register offset 0x8 via reconfig_cpri interface.
  5. Release the reset for deterministic measure logic for RX datapath by clearing rx_dl_restart bit at register offset 0x8 via reconfig_cpri interface.
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