F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 10/04/2021
Public

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Document Table of Contents

4.1. Reset Logic

There are three main user accessible reset ports:
  • i_tx_rst_n—reset the TX datapath.
  • i_rx_rst_n—reset the RX datapath.
  • i_reconfig_reset—reset the Avalon® memory-mapped interface connections to PCS + PMA CSRs, and soft IP CSR.
Figure 7. Reset Block Diagram