Visible to Intel only — GUID: mwh1416946969858
Ixiasoft
Visible to Intel only — GUID: mwh1416946969858
Ixiasoft
13.2.2.3. Memory-Mapped Slave Information
Configuration Name | Type | Default | Meaning | Examples |
---|---|---|---|---|
isMemoryDevice | boolean | 0 | The slave port provides access to a memory device. | Intel FPGA® On-Chip Memory Component, DDR Controller, erasable programmable configurable serial (EPCS) Controller |
isPrintableDevice | boolean | 0 | The slave port provides access to a character-based device. | Intel FPGA UART, Intel FPGA JTAG UART, Intel FPGA LCD |
isTimerDevice | boolean | 0 | The slave port provides access to a timer device. | Intel FPGA Timer |
isEthernetMacDevice | boolean | 0 | The slave port provides access to an Ethernet media access control (MAC). | Intel FPGA Triple-Speed Ethernet |
isNonVolatileStorage 10 | boolean | 0 | The memory device is a non-volatile memory device. The contents of a non-volatile memory device are fixed and always present. In normal operation, you can only read from this memory. If this property is true, you must also set isMemoryDevice to true. | Common flash interface (CFI) Flash, EPCS Flash, on-chip FPGA memory configured as a ROM |
isFlash | boolean | 0 | The memory device is a flash memory device. If isFlash is true, you must also set isMemoryDevice and isNonVolatileStorage to true. | CFI Flash, EPCS Flash |
hideDevice | boolean | 0 | Do not make this slave port visible to the embedded software tools. | Nios® II debug slave port |
affectsTransactionsOnMasters | string | empty string |
A list of master names delimited by spaces, for example m1 m2. Used when the slave port provides access to Avalon-MM control registers in the component. The control registers control transfers on the specified master ports. The slave port can configure the control registers for master ports on the listed components. The address space for this slave port is composed of the address spaces of the named master ports. Nios II embedded software tools use this information to generate #define directives describing the address space of these master ports. |
Intel FPGA direct memory access (DMA), Intel FPGA Scatter/Gather DMA |