Visible to Intel only — GUID: mwh1416946914972
Ixiasoft
Visible to Intel only — GUID: mwh1416946914972
Ixiasoft
8.4. Debugging Nios II ISRs
With the IIC, the ipending register (ctl4) is masked to all zeros during single-stepping. This masking prevents the processor from servicing interrupts that are asserted while you single-step through code. As a result, if you try to single-step through a part of the exception handling system that reads the ipending register, such as alt_irq_entry() or alt_irq_handler(), the code does not detect any pending interrupts. This issue does not affect debugging software exceptions. You can set breakpoints in your ISR code (and single-step through it), because the interrupt funnel has already used ipending to determine which device caused the hardware interrupt.