Visible to Intel only — GUID: mwh1416946885583
Ixiasoft
Visible to Intel only — GUID: mwh1416946885583
Ixiasoft
8.1.3.4. How an External Interrupt Controller Works
With an EIC, the Nios II processor supports an arbitrary number of independent hardware interrupt signals. Interrupts are typically vectored, with interrupt priority levels associated in hardware. Vectoring allows the Nios II processor to transfer control directly to each ISR. Hardware interrupt levels allow the most critical interrupts to pre-empt lower-priority interrupts. Because both of these features are implemented in hardware, the system can handle an interrupt without executing general exception funnel code.
For more information, refer to an example of an EIC implementation in the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.
- Directly to the Nios II EIC interface
- Through the daisy-chain port on another EIC