F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Download PDF
ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.4.1. Simulating the Design Example Testbench

Figure 10. Procedure
Follow these steps to simulate the testbench:
  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench: 
    cd <my_design>/example_testbench
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench received five hyperframes, and displays "PASSED".
    Table 9.  Steps to Simulate the Testbench
    Simulator Instructions
    Riviera Instructions - In the command line, type: vsim -c -do run_rivierasim.do
    VCS* In the command line, type:
    sh run_vcs.sh
    VCS* MX In the command line, type:
    sh run_vcsmx.sh
    QuestaSim* or Questa* Intel® FPGA Edition In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type: 
    vsim -c -do run_vsim.do
    Xcelium* In the command line, type:
    sh run_xcelium.sh
    The following sample output illustrates a successful simulation test run for 24.33024 Gbps with 4 CPRI channels: 
    Ref clock is 184.32 MHz
Waiting for TX ready
TX is ready is high at time              75250000
Waiting for RX ready
RX is ready is high at time             120750000
*** configure DL ***
** Address offset = 0x185d, ReadData  = 0x00000a86
** Address offset = 0x3c00a, ReadData  = 0x000c0000
** Address offset = 0x3c00a, WriteData = 0x000c0a86
** Address offset = 0x3c00a, ReadData  = 0x000c0a86
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x000034a6
** Address offset = 0x3c008, ReadData  = 0x000c0000
** Address offset = 0x3c008, WriteData = 0x000c34a6
** Address offset = 0x3c008, ReadData  = 0x000c34a6
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x00003526
** Address offset = 0x3c006, ReadData  = 0x014c0000
** Address offset = 0x3c006, WriteData = 0x014c3526
** Address offset = 0x3c006, ReadData  = 0x014c3526
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x00001be6
** Address offset = 0x3c004, ReadData  = 0x014c0000
** Address offset = 0x3c004, WriteData = 0x014c1be6
** Address offset = 0x3c004, ReadData  = 0x014c1be6
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
*** sending packets in progress, waiting for checker pass ***
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001ba0
** Address offset = 0x4, ReadData  = 0x000082bf
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385120ns: Channel 0: Round trip measure done with count 5151
** Channel 0: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001b44
** Address offset = 0x4, ReadData  = 0x00008516
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385255ns: Channel 1: Round trip measure done with count 5216
** Channel 1: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001b02
** Address offset = 0x4, ReadData  = 0x0000860c
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385385ns: Channel 2: Round trip measure done with count 5240
** Channel 2: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001a79
** Address offset = 0x4, ReadData  = 0x000083d7
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 387084ns: Channel 3: Round trip measure done with count 5152
** Channel 3: RX checker has received packets correctly!
** PASSED
**
*****************************************
$finish called from file "basic_avl_tb_top.sv", line 352.
$finish at simulation time 387104ns
Level Two Title