F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.4.2. Simulating the Design Example Testbench Simplified Model

When enabling the "simplified IP core model in simulation (Support 24G non-FEC only)" option, an additional folder named "example_testbench_simple_model" is generated alongside the regular files of the generated standard example design. This streamlined testbench enables users to simulate the standard testbench flow in a shorter duration. However, please note that this simplified model does not include the Deterministic Latency feature or serial functionality. It specifically supports a speed rate of 24G non-FEC without the 8B10B reconfiguration option.

Figure 11. Procedure
Follow these steps to simulate the testbench:
  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench_simple_model: 
    cd <my_design>/example_testbench_simple_model
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Simplified Testbench.
  3. Analyze the results. The successful testbench displays "PASSED".

    To execute the testbench, use one of the commands below, depending on the simulator.

    Table 10.  Steps to Simulate the Simplified Testbench
    Simulator Instructions
    VCS* In the command line, type:
    sh run_vcs.sh
    QuestaSim* or Questa* Intel® FPGA Edition In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type: 
    vsim -c -do run_vsim.do
    Xcelium* In the command line, type:
    sh run_xcelium.sh
    Riviera In the command line, type:
    vsim -c -do run_riviera.do
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