F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.09.30 24.3 5.0.0
  • Added support for Device initialization clock in the Example Design tab
  • Added Riviera support
2024.08.15 24.2 4.3.3 Added Analog Parameter Settings
2023.12.04 23.4 4.3.1
  • Added support for Simulating the Design Example Testbench simplified model.
  • Added device initialization clock preset for devkit in the generated Design Example.
2023.10.02 23.3 4.3.0 In the Generating the Design section, added the Analog Parameters information.
2023.03.14 23.1 4.0.0
  • Updated the product family name to "Intel Agilex 7."
2022.09.26 22.3 4.0.0
  • Added support for new reference clock (122.88 MHz).
    • Updated the Figure: Block Diagram.
    • Updated the Interface Signals sections.
2022.06.21 22.2 3.3.0
  • Added the hardware design example support for:
    • Intel Agilex I-Series FPGA Development Kit
    • Intel Agilex I-Series Transceiver-SoC Development Kit
  • Updated the Hardware and Software Requirements section.
2022.03.28 22.1 3.2.0
  • Removed support for ModelSim* SE simulator.
  • Updated the SIM_MODE parameter description in section: Packet Client.
2021.12.13 21.4 3.1.0
  • Added support for Cadence Xcelium* simulator.
  • Added support for Transceiver Toolkit.
  • Added new section: Design Example Components.
2021.10.04 21.3 3.0.0
  • Added support for new simulators in section: Hardware and Software Requirements.
  • Updated steps in section: Simulating the Design Example Testbench.
  • Updated the following sections with new line rate information:
    • Design Example Description
    • Simulation Design Example
    • Interface Signals
  • Updated the address in section: Design Example Registers.
2021.06.21 21.2 2.0.0 Initial release.
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