F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.4. F-Tile CPRI IP Hardware Design Example

Figure 13. F-Tile CPRI IP Design Example Block Diagram
  1. For CPRI designs with CPRI line rate 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps use 8b/10b interface. For CPRI designs with CPRI line rates 10.1,12.1, and 24.3 Gbps with and without RS-FEC use MII.
  2. Transceiver reference clock:
    • 122.88 MHz: For all CPRI line rates.
    • 153.6 MHz: For CPRI line rates 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps.
    • 184.32 MHz: For CPRI line rates 10.1,12.1, and 24.3 Gbps with and without RS-FEC.
The F-Tile CPRI PHY Intel® FPGA IP hardware design example includes the following components:
  • F-Tile CPRI PHY Intel® FPGA IP.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate the sampling clock for deterministic latency logic inside the IP, and the round trip counter component at testbench.
  • System PLL to generate the system clocks for the IP.
  • Avalon® memory-mapped address decoder to decode reconfiguration address space for CPRI PHY Reconfiguration Interface, PMA Avalon® Memory-Mapped Interface, and Datapath Avalon® Memory-Mapped Interface.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.
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