F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.2.2. Analog Parameters for F-Tile IPs

Analog parameter settings allow you to tune the transceiver analog functions in the FGT and FHT PMAs while designing high-speed serial protocol solutions. Use this feature to compensate for signal losses for high data rate communication.
Note: The design level HSSI_PARAMETER settings in the .qsf file take precedence over the Analog Parameters GUI settings.
Figure 7. Analog Parameter Options for FGT PMA in Parameter Editor
Table 2.  FGT TX Equalization (EQ) Analog Parameter Options
Parameter Values Description
FGT TXEQ Post Tap 1, 1.0 step size 0 to 19 Options for FGT TX EQ Post Tap 1, in 1.0 step size increments. Default value is 0.
FGT TXEQ Pre Tap 1, 1.0 step size 0 to 15 Options for FGT TX EQ Pre Tap 1, in 1.0 step size increments. Default value is 5.
FGT TXEQ Pre Tap 2, 1.0 step size 0 to 7

Options for FGT TX EQ Pre Tap 2, in 1.0 step size increments. Default value is 0.

FGT TXEQ Main Tap, 1.0 step size 0 to 55 Options for FGT TX EQ Main Tap, in 1.0 step size increments. Default value is 35.
Table 3.  FGT RX Analog Parameter Options
Parameter Values Description
Select FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_1(85 Ohms)

RX_ONCHIP_TERMINATION_R_2(100 ohms)

Selects FGT RX termination resistor setting. Default value is RX_ONCHIP_TERMINATION_R_2(100 ohms).
Enable FGT RX AC Couple DISABLE

ENABLE

Enable RX external AC coupling setting. Default value is ENABLE.
Enable FGT VSR mode VSR_MODE_LOW_LOSS

VSR_MODE_HIGH_LOSS

VSR_MODE_DISABLE

Enable VSR mode setting. Default value is VSR_MODE_DISABLE.
RXEQ VGA Gain 0 to 63 Options for RX EQ VGA gain value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
RXEQ High Frequency Boost 0 to 63 Options for RX EQ high frequency boost value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
RXEQ DFE Data Tap1 0 to 63 Options for RX EQ DFE data tap1 value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
Figure 8. Analog Parameter Options for FHT PMA in Parameter Editor
Table 4.  FHT TX Analog Parameter Options
Parameter Values Description
Enable FHT TX P&N Invert Disabled

Enabled

Enable FHT TX P and N inversion. Default value is Disabled.
Enable FHT TXOUT Tristate Disabled

Enabled

Enable tristate on FHT TX serial outputs. Default value is Disabled.
Select FHT TX Termination TXTERM_OFFSET_P0(90 Ohms)

TXTERM_OFFSET_M1(96.8 Ohms)

Selects FHT TX termination resistor setting. Default value is TXTERM_OFFSET_P0(90 Ohms).
Table 5.  FHT TX Equalization (EQ) Analog Parameter Options
Parameter Values Description

Post-Cursor 4, 0.25 step size

-8.0 to +7.75 FHT post tap 4 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 3, 0.25 step size -8.0 to +7.75 FHT post tap 3 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 2, 0.25 step size -8.0 to +7.75 FHT post tap 2 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 1, 0.5 step size -16.0 to +15.5 FHT post tap 1 coefficient, 0.5 step size. Default value is 0.0.
Main-Cursor,0.5 step size 0.0 to 41.5 FHT main tap coefficient, 0.5 step size. Default value is 41.5.
Pre-Cursor 1,0.5 step size -16.0 to +15.5 FHT pre tap 1 coefficient, 0.5 step size. Default value is 0.0.
Pre-Cursor 2,0.25 step size -8.0 to +7.75 FHT pre tap 2 coefficients, 0.25 step size. Default value is 0.0.
Pre-Cursor 3,0.25 step size -8.0 to +7.75 FHT pre tap 3 coefficients, 0.25 step size. Default value is 0.0.
Table 6.  FHT RX Analog Parameter Options
Parameter Values Description
Enable FHT RX P&N Invert Disabled

Enabled

Enable FHT RX P and N inversion. Default value is Disabled.
Select FHT RX Termination RXTERM_OFFSET_P0(90 Ohms)

RXTERM_OFFSET_P2(94.6 Ohms)

RXTERM_OFFSET_P3(97.7 Ohms)

RXTERM_OFFSET_P4(100 Ohms)

RXTERM_OFFSET_P5(102.3 Ohms)

RXTERM_OFFSET_P6(105.4 Ohms)

RXTERM_OFFSET_P7(107.7 Ohms)

RXTERM_OFFSET_P8(110 Ohms)

RXTERM_OFFSET_M4(80.8 Ohms)

RXTERM_OFFSET_M5(83.1 Ohms)

RXTERM_OFFSET_M6(85.4 Ohms)

RXTERM_OFFSET_M7(87.7 Ohms)

Selects FHT RX termination resistor setting. Default value is RXTERM_OFFSET_P0(90 Ohms).
Select FHT external AC Cap EXTERNAL_AC_CAP_ENABLE

EXTERNAL_AC_CAP_DISABLE

Enable external AC coupling capacitance. Default value is EXTERNAL_AC_CAP_ENABLE.
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