F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The F-Tile CPRI PHY Intel® FPGA IP design example file directories contain the following generated files for the design example:
Figure 9. Directory Structure of the Generated Example Design
Table 7.  Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the hardware design example module and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/cpriphy_ftile_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/example_testbench/cpriphy_ftile_hw.sv Hardware design example module that instantiates DUT and other testbench components.

Testbench Scripts1

<design_example_dir>/example_testbench/run_riviera.do The Riviera script to run the testbench
<design_example_dir>/example_testbench/run_vsim.do The Siemens* EDA QuestaSim* , or Questa* Intel® FPGA Edition script to run the testbench.

<design_example_dir>/example_testbench/run_vcs.sh

The Synopsys* VCS* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
<design_example_dir>/example_testbench/run_xcelium.sh The Cadence Xcelium* script to run the testbench.
Table 8.   Hardware Design Example File Descriptions
File Names Descriptions
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qpf Quartus® Prime project file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qsf Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Agilex™ 7 device.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.v Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/hardware_test_design/hwtest_sl/main_script.tcl Main file for accessing System Console.
1 Ignore any other simulator script in the <design_example_dir>/example_testbench/ folder.
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