F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Analog Parameters Tab
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.2. Generating the Design Example

Follow these steps to generate the F-Tile CPRI PHY IP hardware design example and testbench.
Figure 2. Example Design Tab in IP Parameter Editor
  1. Create an Quartus® Prime Pro Edition project:
    1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new project, or File > Open Project to open an existing project. The wizard prompts you to specify a device.
    2. Specify the device family Agilex™ 7 (I-series) and select a device that meets all of these requirements:
      • Transceiver tile: F-tile
      • Transceiver speed grade: -1 or -2
      • Core speed grade: -1 or -2 or -3
    3. Click Finish.
  2. In the IP Catalog, locate and select F-Tile CPRI PHY Intel® FPGA IP. The New IP Variation dialog box appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation.
  6. On the Example Design tab:
    1. Under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
    2. Under Generated HDL Format, select Verilog HDL or VHDL. If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_<datarate> directory is a VHDL model, but the main testbench file is a SystemVerilog file.
    3. Under Target Development Kit, select your board.
    4. Turn on Simplified testbench for a testbench that allows you to emulate the simulation flow of the standard testbench with shorter simulation time.
      This simplified testbench does not provide deterministic latency or the serial functionality, and supports only 24G non-FEC speed rate without 8B10B reconfiguration option.
  7. On the Analog Parameters tab, select the correct parameters for your design example. Refer to Analog Parameters Tab
  8. Click the Generate Example Design button. The Select Example Design Directory dialog box appears.
  9. To modify the design example directory path or name from the defaults (cpriphy_ftile_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).

Section Content
Analog Parameters Tab

Level Two Title