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1.1. Hardware and Software Requirements
1.2. Generating the Design Example
1.3. Directory Structure
1.4. Simulating the Design Example
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
1.8. Transceiver Toolkit
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Ixiasoft
2. Design Example Description
The design example demonstrates the basic functionality of the F-Tile CPRI PHY Intel® FPGA IP core. You can generate the design from the Example Design tab in the F-Tile CPRI PHY Intel® FPGA IP parameter editor.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. You can choose to generate the design example with or without the RS-FEC feature. The RS-FEC feature is available with 10.1376, 12.1651, and 24.33024 Gbps CPRI line bit rates.
CPRI Line Bit Rate (Gbps) | RS-FEC Support | Reference Clock (MHz) | Deterministic Latency Support |
---|---|---|---|
1.2288 | No | 153.6 or 122.88 | Yes |
2.4576 | No | 153.6 or 122.88 | Yes |
3.072 | No | 153.6 or 122.88 | Yes |
4.9152 | No | 153.6 or 122.88 | Yes |
6.144 | No | 153.6 or 122.88 | Yes |
9.8304 | No | 153.6 or 122.88 | Yes |
10.1376 | With and Without | 184.32 or 122.88 | Yes |
12.1651 | With and Without | 184.32 or 122.88 | Yes |
24.33024 | With and Without | 184.32 or 122.88 | Yes |