2.2.2. Round Trip Counter
A Round Trip Counter is a simple counter that measures the duration between two pulses. The pulses are always in pairs, called as start, and stop pulse. The pulses are generated by the TX pattern generator and RX pattern checker, respectively. When a start pulse is received, it triggers a counter to start counting. When a stop pulse is received, the counter stops.
The counter value is the number of clock cycles elapsed between the two pulses. To calculate duration in unit time, multiply the counter value by the period of the clock cycle. For accuracy, you can repeat this process multiple times (using a parameter) and obtain the mean average. This average duration between start and stop pulses is called the round trip delay. The round trip delay can be used as a benchmark to check against the Deterministic Latency measurement of F-Tile CPRI PHY Intel FPGA IP, which has its own independent measurement. The two measurements must not differ by +/- 3ns.
Parameter Name | Default Value | Description |
---|---|---|
COUNT_WIDTH | 8 | Determines the width of counter_out. |
DL_TOT_MEASURE_CNT | 10 | Determines how many pairs of start and stop pulses must be received before asserting measure_done. |
Port Name | Width | Direction | Domain | Description |
---|---|---|---|---|
clk | 1 | Input | - | Clock. Supply with sampling_clk. |
reset | 1 | Input | clk | Synchronous Reset. Active high. |
cpri_rate_sel | 4 | Input | clk | Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP. |
start | 1 | Input | clk | Start pulse to start the internal counter. |
stop | 1 | Input | clk | Stop pulse to stop the internal counter. |
measure_done | 1 | Output | clk | An indicator that is asserted when a set number of pairs of start/stop pulses (specified by DL_TOT_MEASURE_CNT) have been received. |
trigger_recount | 1 | Output | clk | An indicator that is asserted when a start and stop pulse pair is received, and RT counter is ready to receive the next pair. |
counter_out | COUNT_WIDTH | Output | clk | The total duration of all the start and stop pulses in terms of clock cycles. |
The following calculates calculate the round trip delay:
Round Trip Delay = (counter_out * clk period) / DL_TOT_MEASURE_CNT
where:
- clk period = sampling_clk period = 1/250 MHz = 4ns
- DL_TOT_MEASURE_CNT = 128 (for hardware) or 32 (for simulation)