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1.1. Hardware and Software Requirements
1.2. Generating the Design Example
1.3. Directory Structure
1.4. Simulating the Design Example
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
1.8. Transceiver Toolkit
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Ixiasoft
1.4.1. Simulating the Design Example Testbench
Figure 8. Procedure
Follow these steps to simulate the testbench:
- At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench:
cd <my_design>/example_testbench
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
- Analyze the results. The successful testbench received five hyperframes, and displays "PASSED".
Table 4. Steps to Simulate the Testbench Simulator Instructions VCS* In the command line, type: sh run_vcs.sh
VCS* MX In the command line, type: sh run_vcsmx.sh
QuestaSim* or Questa* Intel® FPGA Edition In the command line, type: vsim -do run_vsim.do
If you prefer to simulate without bringing up the GUI, type:vsim -c -do run_vsim.do
Xcelium* In the command line, type: sh run_xcelium.sh
The following sample output illustrates a successful simulation test run for 24.33024 Gbps with 4 CPRI channels:Ref clock is 184.32 MHz Waiting for TX ready TX is ready is high at time 75250000 Waiting for RX ready RX is ready is high at time 120750000 *** configure DL *** ** Address offset = 0x185d, ReadData = 0x00000a86 ** Address offset = 0x3c00a, ReadData = 0x000c0000 ** Address offset = 0x3c00a, WriteData = 0x000c0a86 ** Address offset = 0x3c00a, ReadData = 0x000c0a86 ** Address offset = 0x2, WriteData = 0xc0000000 ** Address offset = 0x2, WriteData = 0x00000000 ** Address offset = 0x185d, ReadData = 0x000034a6 ** Address offset = 0x3c008, ReadData = 0x000c0000 ** Address offset = 0x3c008, WriteData = 0x000c34a6 ** Address offset = 0x3c008, ReadData = 0x000c34a6 ** Address offset = 0x2, WriteData = 0xc0000000 ** Address offset = 0x2, WriteData = 0x00000000 ** Address offset = 0x185d, ReadData = 0x00003526 ** Address offset = 0x3c006, ReadData = 0x014c0000 ** Address offset = 0x3c006, WriteData = 0x014c3526 ** Address offset = 0x3c006, ReadData = 0x014c3526 ** Address offset = 0x2, WriteData = 0xc0000000 ** Address offset = 0x2, WriteData = 0x00000000 ** Address offset = 0x185d, ReadData = 0x00001be6 ** Address offset = 0x3c004, ReadData = 0x014c0000 ** Address offset = 0x3c004, WriteData = 0x014c1be6 ** Address offset = 0x3c004, ReadData = 0x014c1be6 ** Address offset = 0x2, WriteData = 0xc0000000 ** Address offset = 0x2, WriteData = 0x00000000 *** sending packets in progress, waiting for checker pass *** *** waiting for measure_valid to assert... ** Address offset = 0x2, ReadData = 0x00000003 ** measure_valid is asserted. ** Address offset = 0x3, ReadData = 0x00001ba0 ** Address offset = 0x4, ReadData = 0x000082bf *** waiting for hyperframe sync to assert... ** hyperframe sync is asserted. *** waiting for round trip measure... -> 385120ns: Channel 0: Round trip measure done with count 5151 ** Channel 0: RX checker has received packets correctly! ** PASSED *** waiting for measure_valid to assert... ** Address offset = 0x2, ReadData = 0x00000003 ** measure_valid is asserted. ** Address offset = 0x3, ReadData = 0x00001b44 ** Address offset = 0x4, ReadData = 0x00008516 *** waiting for hyperframe sync to assert... ** hyperframe sync is asserted. *** waiting for round trip measure... -> 385255ns: Channel 1: Round trip measure done with count 5216 ** Channel 1: RX checker has received packets correctly! ** PASSED *** waiting for measure_valid to assert... ** Address offset = 0x2, ReadData = 0x00000003 ** measure_valid is asserted. ** Address offset = 0x3, ReadData = 0x00001b02 ** Address offset = 0x4, ReadData = 0x0000860c *** waiting for hyperframe sync to assert... ** hyperframe sync is asserted. *** waiting for round trip measure... -> 385385ns: Channel 2: Round trip measure done with count 5240 ** Channel 2: RX checker has received packets correctly! ** PASSED *** waiting for measure_valid to assert... ** Address offset = 0x2, ReadData = 0x00000003 ** measure_valid is asserted. ** Address offset = 0x3, ReadData = 0x00001a79 ** Address offset = 0x4, ReadData = 0x000083d7 *** waiting for hyperframe sync to assert... ** hyperframe sync is asserted. *** waiting for round trip measure... -> 387084ns: Channel 3: Round trip measure done with count 5152 ** Channel 3: RX checker has received packets correctly! ** PASSED ** ***************************************** $finish called from file "basic_avl_tb_top.sv", line 352. $finish at simulation time 387104ns