The packet client, also known as the pattern generator/checker, is used for the following purposes:
- Generate CPRI hyperframe at the TX, and check the hyperframe for correctness at the RX.
- Generate start pulses at the TX, and stop pulses at the RX, for deterministic latency measurement.
There are two types of packet client:
- XGMII—used for 64b/66b data rates, like 24G, 12G, and 10G.
- 8B/10B—used for data rates, like 9.8G, 6.1G, 4.9G, 2.4G, and 1.2G
The structure of the generated pattern at TX is a simple hyperframe structure that consists of two parts: the synchronization control word, and the data block. The generated pattern does not contain any other control words as specified in
Table 7 of CPRI Specification v7.0, which is useful when decoding the frame at the MAC level.
The hyperframe starts by sending synchronization control words, which is specified in Table 9A of CPRI Specification v7.0 (for XGMII) or Table 9 of CPRI Specification v7.0 (for 8B/10B). Followed by data block, which consists of an incremental pattern from a counter (for XGMII), or PRBS pattern (for 8B/10B). The size of the hyperframe also honors the variable word length that varies with data rate, as specified in Table 3 of CPRI Specification v7.0.
At the RX, the pattern checker receives the hyperframe and determines whether it achieve HFNSYNC according to Figure 26B of CPRI Specification v7.0 (for XGMII), or Figure 26A of CPRI Specification v7.0 (for 8B/10B). Once HFNSYNC is achieved, the pattern checker checks the data pattern at the data block for correctness.
Table 7. XGMII Pattern Generator Ports
Port Name |
Width |
Direction |
Domain |
Description |
clk |
1 |
Input |
- |
Clock. Supply with tx_clkout2. |
reset |
1 |
Input |
async |
Asynchronous reset. Active high. |
cpri_rate_sel |
4 |
Input |
clk |
Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP. |
tx_dataout |
64 |
Output |
clk |
TX XGMII data. |
tx_ctrlout |
8 |
Output |
clk |
TX XGMII control. |
start |
1 |
Output |
clk |
Start pulse used for deterministic latency measurement. |
Table 8. XGMII Pattern Generator Parameters
Parameter Name |
Default Value |
Description |
SIM_MODE |
0 |
When enabled, the generated hyperframe size is reduced by a factor of 4 or 64, thereby reducing the simulation time.
- 0: disabled
- 1: enabled (reduced by a factor of 4)
- 2: enabled (reduced by a factor of 64)
|
Table 9. XGMII Pattern Checker Ports
Port Name |
Width |
Direction |
Domain |
Description |
clk |
1 |
Input |
- |
Clock. Supply with rx_clkout2. |
nreset |
1 |
Input |
async |
Asynchronous reset. Active low. |
cpri_rate_sel |
4 |
Input |
clk |
Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP. |
datain |
DATA_WIDTH |
Input |
clk |
RX XGMII data. |
ctrl |
8 |
Input |
clk |
RX XGMII control. |
hyperframe_sync |
1 |
Output |
clk |
Indicates whether RX has achieved HFNSYNC. |
errorflag |
1 |
Output |
clk |
Asserted when err_cnt is not 0 and latches until being reset. |
err_cnt |
5 |
Output |
clk |
Error counter that is incremented by 1 when 1 cycle of received data pattern is mismatched. |
stop |
1 |
Output |
clk |
Stop pulse used for deterministic latency measurement. |
Table 10. XGMII Pattern Checker Parameters
Parameter Name |
Default Value |
Description |
SIM_MODE |
0 |
When enabled, this parameter guides checker to look for the correct position in the shorter hyperframe (enabled by similar setting in TX) when searching for the sync control word.
- 0: disabled
- 1: enabled (reduced by a factor of 4)
- 2: enabled (reduced by a factor of 64)
|
DATA_WIDTH |
8 |
Determines the width of datain. |
Table 11. 8B/10B Pattern Generator Ports
Port Name |
Width |
Direction |
Domain |
Description |
clk |
1 |
Input |
- |
Clock. Supply with tx_clkout2. |
reset |
1 |
Input |
async |
Asynchronous reset. Active high. |
cpri_rate_sel |
4 |
Input |
clk |
Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP. |
tx_dataout |
DATA_WIDTH |
Output |
clk |
TX 8B/10B data. |
tx_ctrlout |
DATA_WIDTH/8 |
Output |
clk |
TX 8B/10B control. |
start |
1 |
Output |
clk |
Start pulse used for deterministic latency measurement. |
Table 12. 8B/10B Pattern Generator Parameters
Parameter Name |
Default Value |
Description |
SIM_MODE |
0 |
When enabled, the generated hyperframe size is reduced by a factor of 4 or 64, thereby reducing the simulation time.
- 0: disabled
- 1: enabled (reduced by a factor of 4. Start/stop pulses feature is supported.)
- 2: enabled (reduced by a factor of 64. Start/stop pulses feature is not supported.)
|
DATA_WIDTH |
16 |
Determines the width of tx_dataout and tx_ctrlout. |
Table 13. 8B/10B Pattern Checker Ports
Port Name |
Width |
Direction |
Domain |
Description |
clk |
1 |
Input |
- |
Clock. Supply with rx_clkout2. |
nreset |
1 |
Input |
async |
Asynchronous reset. Active low. |
cpri_rate_sel |
4 |
Input |
clk |
Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP. |
datain |
DATA_WIDTH |
Input |
clk |
RX 8B/10B data. |
ctrl |
DATA_WIDTH/8 |
Input |
clk |
RX 8B/10B control. |
hyperframe_sync |
1 |
Output |
clk |
Indicates whether RX has achieved HFNSYNC. |
errorflag |
1 |
Output |
clk |
Asserted when err_cnt is not 0 and latches until being reset. |
err_cnt |
5 |
Output |
clk |
Error counter that is incremented by 1 when 1 cycle of received data pattern is mismatched. |
stop |
1 |
Output |
clk |
Stop pulse used for deterministic latency measurement. |
Table 14. 8B/10B Pattern Checker Parameters
Parameter Name |
Default Value |
Description |
SIM_MODE |
0 |
When enabled, this parameter guides checker to look for the correct position in the shorter hyperframe (enabled by similar setting in TX) when searching for the sync control word.
- 0: disabled
- 1: enabled (reduced by a factor of 4. Start/stop pulses feature is supported.)
- 2: enabled (reduced by a factor of 64. Start/stop pulses feature is not supported.)
|
DATA_WIDTH |
16 |
Determines the width of datain and ctrl. |