DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.10.2.3. VIDEO_MODE_BANK_SELECT (0x53)

Table 138.  VIDEO_MODE_BANK_SELECT (0x53)
Name Bit(s) Access Description Reset
Video mode bank select 31:0 RW Writes to the video mode registers (0x54-0x6D) reflect to the video mode bank selected by this one-hot register. Only 1 mode bank is available. Writes 0x1 to this register to select mode bank 1. 0x0