DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.3.1. DPTX_PRE_VOLT0/DPTX_REG_TXFFE0

These ports drive the respective tx_vod, tx_emp ports (8B/10B channel coding), and tx_reconfig_ffe0 (128B/132B channel coding).

Address: 0x0010

Direction: RW

Reset: 0x00000000

Table 81.  DPTX_PRE_VOLT0/DPTX_REG_TXFFE0 Bits

Bit

Bit Name

Function

31:8

Unused

7:4

TX_FFE0

128B/132B Channel Coding:

Tx FFE Preset on lane 0

3:2

PRE0

8B/10B Channel Coding:

Pre-emphasis output on lane 0

1:0

VOLT0

8B/10B Channel Coding:

Voltage swing output on lane 0