DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.3.12. DPTX_TEST_264BIT_PATTERN7

Address: 0x001B

Direction: RW

Reset: 0x00000000

Table 92.  DPTX_TEST_264BIT_PATTERN7 Bits

Bit

Bit Name

Function

31:0

264BIT_PATTERN7

Bits 223:192 of the 264 bit custom pattern for PHY compliance test.