1.12. Power Management
Stratix V devices leverage FPGA architectural features and process technology advancements to reduce total power consumption by up to 30% when compared with Stratix IV devices at the same performance level.
Stratix V devices continue to provide programmable power technology, introduced in earlier generations of Stratix FPGA families. The Quartus II software PowerPlay feature identifies critical timing paths in a design and biases core logic in that path for high performance. PowerPlay also identifies non-critical timing paths and biases core logic in that path for low power instead of high performance. PowerPlay automatically biases core logic to meet performance and optimize power consumption.
Additionally, Stratix V devices have a number of hard IP blocks that reduce logic resources and deliver substantial power savings when compared with soft implementations. The list includes PCIe Gen1/Gen2/Gen3, Interlaken PCS, hard I/O FIFOs, and transceivers. Hard IP blocks consume up to 50% less power than equivalent soft implementations.
Stratix V transceivers are designed for power efficiency. The transceiver channels consume 50% less power than Stratix IV FPGAs. The transceiver PMA consumes approximately 90 mW at 6.5 Gbps and 170 mW at 12.5 Gbps.