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1.1. Stratix V Family Variants
1.2. Stratix V Features Summary
1.3. Stratix V Family Plan
1.4. Low-Power Serial Transceivers
1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
1.6. External Memory and GPIO
1.7. Adaptive Logic Module
1.8. Clocking
1.9. Fractional PLL
1.10. Embedded Memory
1.11. Variable Precision DSP Block
1.12. Power Management
1.13. Incremental Compilation
1.14. Enhanced Configuration and CvP
1.15. Automatic Single Event Upset Error Detection and Correction
1.16. HardCopy V Devices
1.17. Ordering Information
1.18. Document Revision History
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1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
Stratix V devices have PCIe hard IP designed for performance, ease-of-use, and increased functionality. The PCIe hard IP consists of the PCS, data link, and transaction layers. The PCIe hard IP supports Gen3, Gen2, and Gen1 end point and root port up to x8 lane configurations.
The Stratix V PCIe hard IP operates independently from the core logic, which allows the PCIe link to wake up and complete link training in less than 100 ms while the Stratix V device completes loading the programming file for the rest of the FPGA. The PCIe hard IP also provides added functionality, which helps support emerging features such as Single Root I/O Virtualization (SR-IOV) or optional protocol extensions. In addition, the Stratix V device PCIe hard IP has improved end-to-end data path protection using ECC and enables device CvP.
In all Stratix V devices, the primary PCIe hard IP that supports CvP is always in the bottom left corner of the device (IOBANK_B0L) when viewing the die from the top.