Stratix V Device Overview

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ID 683258
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Stratix V Device Overview
1. Stratix V Device Overview x
1.1. Stratix V Family Variants 1.2. Stratix V Features Summary 1.3. Stratix V Family Plan 1.4. Low-Power Serial Transceivers 1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block) 1.6. External Memory and GPIO 1.7. Adaptive Logic Module 1.8. Clocking 1.9. Fractional PLL 1.10. Embedded Memory 1.11. Variable Precision DSP Block 1.12. Power Management 1.13. Incremental Compilation 1.14. Enhanced Configuration and CvP 1.15. Automatic Single Event Upset Error Detection and Correction 1.16. HardCopy V Devices 1.17. Ordering Information 1.18. Document Revision History
1.14. Enhanced Configuration and CvP x
1.14.1. Partial Reconfiguration
1. Stratix V Device Overview

1.14.1. Partial Reconfiguration

Partial reconfiguration allows you to reconfigure part of the FPGA while other sections continue to operate.

This capability is required in systems where uptime is critical because partial reconfiguration allows you to make updates or adjust functionality without disrupting services. While lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place FPGA functions that do not operate simultaneously. Instead, you can store these functions in external memory and load them as required. This capability reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.

You no longer need to know all the details of the FPGA architecture to perform partial reconfiguration. Altera simplifies the process by extending the power of incremental compilation used in earlier versions of the Quartus II software.

Partial reconfiguration is supported in the following configurations:

  • Partial reconfiguration through the FPP x16 I/O interface
  • CvP
  • Soft internal core, such as the Nios® II processor.
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