Stratix V Device Overview

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ID 683258
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Stratix V Device Overview
1. Stratix V Device Overview x
1.1. Stratix V Family Variants 1.2. Stratix V Features Summary 1.3. Stratix V Family Plan 1.4. Low-Power Serial Transceivers 1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block) 1.6. External Memory and GPIO 1.7. Adaptive Logic Module 1.8. Clocking 1.9. Fractional PLL 1.10. Embedded Memory 1.11. Variable Precision DSP Block 1.12. Power Management 1.13. Incremental Compilation 1.14. Enhanced Configuration and CvP 1.15. Automatic Single Event Upset Error Detection and Correction 1.16. HardCopy V Devices 1.17. Ordering Information 1.18. Document Revision History
1.14. Enhanced Configuration and CvP x
1.14.1. Partial Reconfiguration
1. Stratix V Device Overview

1.7. Adaptive Logic Module

Stratix V devices use an improved ALM to implement logic functions more efficiently. The Stratix V ALM has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

The Stratix V ALM has the following enhancements:

  • Packs 6% more logic when compared with the ALM found in Stratix IV devices.
  • Implements select 7-input LUT-based functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core usage.
  • Adds more registers (four registers per 8-input fracturable LUT). More registers allow Stratix V devices to maximize core performance at a higher core logic usage and provides easier timing closure for register-rich and heavily pipelined designs.

The Quartus II software leverages the Stratix V ALM logic structure to deliver the highest performance, optimal logic usage, and lowest compile times. The Quartus II software simplifies design re-use because it automatically maps legacy Stratix designs into the new Stratix V ALM architecture.

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