Stratix V Device Overview

ID 683258
Date 6/15/2020
Public

1.9. Fractional PLL

Stratix V devices contain up to 32 fractional PLLs.

You can use the fractional PLLs to reduce both the number of oscillators required on the board and the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In addition, you can use the fractional PLLs for clock network delay compensation, zero delay buffering, and transmitter clocking for transceivers. Fractional PLLs can be individually configured for integer mode or fractional mode with third-order delta-sigma modulation.