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1.1. Stratix V Family Variants
1.2. Stratix V Features Summary
1.3. Stratix V Family Plan
1.4. Low-Power Serial Transceivers
1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
1.6. External Memory and GPIO
1.7. Adaptive Logic Module
1.8. Clocking
1.9. Fractional PLL
1.10. Embedded Memory
1.11. Variable Precision DSP Block
1.12. Power Management
1.13. Incremental Compilation
1.14. Enhanced Configuration and CvP
1.15. Automatic Single Event Upset Error Detection and Correction
1.16. HardCopy V Devices
1.17. Ordering Information
1.18. Document Revision History
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1.15. Automatic Single Event Upset Error Detection and Correction
Stratix V devices offer single event upset (SEU) error detection and correction circuitry that is robust and easy to use.
The correction circuitry includes protection for configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running cyclical redundancy check (CRC) error detection circuit with integrated ECC that automatically corrects one or double-adjacent bit errors and detects higher order multi-bit errors. When more than two errors occur, correction is available through a core programming file reload that refreshes a design while the FPGA is operating.
The physical layout of the FPGA is optimized to make the majority of multi-bit upsets appear as independent single- or double-adjacent bit errors, which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection in Stratix V devices, user memories include integrated ECC circuitry and are layout-optimized to enable error detection of 3-bit errors and correction for 2-bit errors.