1.14. Enhanced Configuration and CvP
Stratix V device configuration is enhanced for ease-of-use, speed, and cost.
Stratix V devices support a new 4-bit bus active serial mode (ASx4). ASx4 supports up to a 400Mbps data rate using small low-cost quad interface Flash devices. ASx4 mode is easy to use and offers an ideal balance between cost and speed. Finally, the fast passive parallel (FPP) interface is enhanced to support 8-, 16-, and 32-bit data widths to meet a wide range of performance and cost goals.
You can configure Stratix V FPGAs using CvP with PCIe. CvP with PCIe divides the configuration process into two parts: the PCIe hard IP and periphery and the core logic fabric. CvP uses a much smaller amount of external memory (flash or ROM) because CvP has to store only the configuration file for the PCIe hard IP and periphery. The 100-ms power-up to active time (for PCIe) is much easier to achieve when only the PCIe hard IP and periphery are loaded. After the PCIe hard IP and periphery are loaded and the root port is booted up, application software running on the root port can send the configuration file for the FPGA fabric across the PCIe link where the file is loaded into the FPGA. The FPGA is then fully configured and functional.
The following table lists the configuration modes available for Stratix V devices.
| Mode |
Fast or Slow POR |
Compression |
Encryption |
Remote Update |
Data Width |
Max Clock Rate (MHz) |
Max Data Rate (Mbps) |
|---|---|---|---|---|---|---|---|
| Active Serial (AS) |
Yes |
Yes |
Yes |
Yes |
1, 4 |
100 |
400 |
| Passive Serial (PS) |
Yes |
Yes |
Yes |
— |
1 |
125 |
125 |
| Fast Passive Parallel (FPP) |
Yes |
Yes |
Yes |
Yes 14 |
8, 16, 32 |
125 15 |
3,000 |
| CvP |
— |
— |
Yes |
Yes |
1, 2, 4, 8 |
— |
3,000 |
| Partial Reconfiguration |
— |
— |
Yes |
Yes |
16 |
125 |
2,000 |
| JTAG |
— |
— |
— |
— |
1 |
33 |
33 |
14 Remote update support with the Parallel Flash Loader.
15 The maximum clock rate is 125 MHz for x8 and x16 FPP, but only 100 MHz for x32 FPP.