ID
683243
Date
10/04/2021
Public
Visible to Intel only — GUID: mwh1410383515225
Ixiasoft
1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Timing Analysis Flow
2.2. Step 1: Specify Timing Analyzer Settings
2.3. Step 2: Specify Timing Constraints
2.4. Step 3: Run the Timing Analyzer
2.5. Step 4: Analyze Timing Reports
2.6. Applying Timing Constraints
2.7. Timing Analyzer Tcl Commands
2.8. Timing Analysis of Imported Compilation Results
2.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
2.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.5.1.1. Report Fmax Summary
2.5.1.2. Report Timing
2.5.1.3. Report Data Delay
2.5.1.4. Report Clocks and Clock Networks
2.5.1.5. Report Clock Transfers
2.5.1.6. Report Logic Depth
2.5.1.7. Report Neighbor Paths
2.5.1.8. Report Register Spread
2.5.1.9. Report Route Net of Interest
2.5.1.10. Report Retiming Restrictions
2.5.1.11. Report Reset Statistics
2.5.1.12. Report Pipelining Information
2.5.1.13. Report Asynchronous CDC
2.5.1.14. Report CDC Viewer
2.5.1.15. Report Time Borrowing Data
2.5.1.16. Report Exceptions and Exceptions Reachability
2.6.1. Recommended Initial SDC Constraints
2.6.2. SDC File Precedence
2.6.3. Modifying Iterative Constraints
2.6.4. Using Entity-bound SDC Files
2.6.5. Creating Clocks and Clock Constraints
2.6.6. Creating I/O Constraints
2.6.7. Creating Delay and Skew Constraints
2.6.8. Creating Timing Exceptions
2.6.9. Using Fitter Overconstraints
2.6.10. Example Circuit and SDC File
2.6.8.5.1. Default Multicycle Analysis
2.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.6.8.5.4. Same Frequency Clocks with Destination Clock Offset
2.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
Visible to Intel only — GUID: mwh1410383515225
Ixiasoft
1. Timing Analysis Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 21.3 |
Comprehensive timing analysis of your design allows you to validate circuit performance, identify timing violations, and drive the Fitter's placement of logic to meet your timing goals. The Intel® Quartus® Prime Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design.
The Timing Analyzer verifies that required timing relationships are met for your design to correctly function, and confirms actual signal arrival times against the constraints that you specify. This user guide provides an introduction to basic timing analysis concepts, along with step-by-step instructions for using the Intel® Quartus® Prime Timing Analyzer.