Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

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ID 683243
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Timing Analysis Introduction 2. Using the Intel® Quartus® Prime Timing Analyzer A. Intel® Quartus® Prime Pro Edition User Guides
1. Timing Analysis Introduction x
1.1. Timing Analysis Basic Concepts 1.2. Timing Analysis Overview Document Revision History
1.1. Timing Analysis Basic Concepts x
1.1.1. Timing Path and Clock Analysis 1.1.2. Clock Setup Analysis 1.1.3. Clock Hold Analysis 1.1.4. Recovery and Removal Analysis 1.1.5. Multicycle Path Analysis 1.1.6. Metastability Analysis 1.1.7. Timing Pessimism 1.1.8. Clock-As-Data Analysis 1.1.9. Multicorner Timing Analysis 1.1.10. Time Borrowing
1.1.1. Timing Path and Clock Analysis x
1.1.1.1. The Timing Netlist 1.1.1.2. Timing Paths 1.1.1.3. Data and Clock Arrival Times 1.1.1.4. Launch and Latch Edges
1.1.5. Multicycle Path Analysis x
1.1.5.1. Multicycle Clock Hold 1.1.5.2. Multicycle Clock Setup
1.1.10. Time Borrowing x
1.1.10.1. Time Borrowing Limitations 1.1.10.2. Time Borrowing with Latches
2. Using the Intel® Quartus® Prime Timing Analyzer x
2.1. Timing Analysis Flow 2.2. Step 1: Specify Timing Analyzer Settings 2.3. Step 2: Specify Timing Constraints 2.4. Step 3: Run the Timing Analyzer 2.5. Step 4: Analyze Timing Reports 2.6. Applying Timing Constraints 2.7. Timing Analyzer Tcl Commands 2.8. Timing Analysis of Imported Compilation Results 2.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 2.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4. Step 3: Run the Timing Analyzer x
2.4.1. Setting the Operating Conditions 2.4.2. Enabling Time Borrowing Optimization
2.5. Step 4: Analyze Timing Reports x
2.5.1. Generating Timing Reports 2.5.2. Cross-Probing with Design Assistant 2.5.3. Launching Design Assistant from Timing Analyzer 2.5.4. Locating Timing Paths in Other Tools 2.5.5. Correlating Constraints to the Timing Report
2.5.1. Generating Timing Reports x
2.5.1.1. Report Fmax Summary 2.5.1.2. Report Timing 2.5.1.3. Report Data Delay 2.5.1.4. Report Clocks and Clock Networks 2.5.1.5. Report Clock Transfers 2.5.1.6. Report Logic Depth 2.5.1.7. Report Neighbor Paths 2.5.1.8. Report Register Spread 2.5.1.9. Report Route Net of Interest 2.5.1.10. Report Retiming Restrictions 2.5.1.11. Report Reset Statistics 2.5.1.12. Report Pipelining Information 2.5.1.13. Report Asynchronous CDC 2.5.1.14. Report CDC Viewer 2.5.1.15. Report Time Borrowing Data 2.5.1.16. Report Exceptions and Exceptions Reachability
2.5.1.8. Report Register Spread x
2.5.1.8.1. Registers with High Timing Path Endpoint Tension 2.5.1.8.2. Registers with High Immediate Fan-Out Tension
2.5.2. Cross-Probing with Design Assistant x
2.5.2.1. Cross-Probing from Design Assistant to Timing Analyzer
2.6. Applying Timing Constraints x
2.6.1. Recommended Initial SDC Constraints 2.6.2. SDC File Precedence 2.6.3. Modifying Iterative Constraints 2.6.4. Using Entity-bound SDC Files 2.6.5. Creating Clocks and Clock Constraints 2.6.6. Creating I/O Constraints 2.6.7. Creating Delay and Skew Constraints 2.6.8. Creating Timing Exceptions 2.6.9. Using Fitter Overconstraints 2.6.10. Example Circuit and SDC File
2.6.1. Recommended Initial SDC Constraints x
2.6.1.1. Create Clock (create_clock) 2.6.1.2. Derive PLL Clocks (derive_pll_clocks) 2.6.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.6.1.4. Set Clock Groups (set_clock_groups)
2.6.4. Using Entity-bound SDC Files x
2.6.4.1. Entity-bound Constraint Scope 2.6.4.2. Entity-bound Constraint Examples
2.6.5. Creating Clocks and Clock Constraints x
2.6.5.1. Creating Base Clocks 2.6.5.2. Creating Virtual Clocks 2.6.5.3. Creating Generated Clocks (create_generated_clock) 2.6.5.4. Deriving PLL Clocks 2.6.5.5. Creating Clock Groups (set_clock_groups) 2.6.5.6. Accounting for Clock Effect Characteristics 2.6.5.7. Constraining CDC Paths
2.6.5.1. Creating Base Clocks x
2.6.5.1.1. Automatic Clock Detection and Constraint Creation
2.6.5.2. Creating Virtual Clocks x
2.6.5.2.1. Specifying I/O Interface Uncertainty 2.6.5.2.2. I/O Interface Clock Uncertainty Example
2.6.5.3. Creating Generated Clocks (create_generated_clock) x
2.6.5.3.1. Clock Divider Example (-divide_by) 2.6.5.3.2. Clock Multiplexer Example
2.6.5.5. Creating Clock Groups (set_clock_groups) x
2.6.5.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 2.6.5.5.2. Asynchronous Clock Groups (-asynchronous) 2.6.5.5.3. set_clock_groups Constraint Tips
2.6.5.6. Accounting for Clock Effect Characteristics x
2.6.5.6.1. Set Clock Latency (set_clock_latency) 2.6.5.6.2. Clock Uncertainty
2.6.6. Creating I/O Constraints x
2.6.6.1. Input Constraints (set_input_delay) 2.6.6.2. Output Constraints (set_output_delay)
2.6.7. Creating Delay and Skew Constraints x
2.6.7.1. Advanced I/O Timing and Board Trace Model Delay 2.6.7.2. Maximum Skew (set_max_skew) 2.6.7.3. Net Delay (set_net_delay)
2.6.8. Creating Timing Exceptions x
2.6.8.1. Timing Exception Precedence 2.6.8.2. False Paths (set_false_path) 2.6.8.3. Minimum and Maximum Delays 2.6.8.4. Multicycle Paths 2.6.8.5. Multicycle Exception Examples 2.6.8.6. Delay Annotation 2.6.8.7. Constraining Design Partition Ports
2.6.8.4. Multicycle Paths x
2.6.8.4.1. Common Multicycle Applications 2.6.8.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.6.8.4.3. Accounting for a Phase Shift (-phase)
2.6.8.5. Multicycle Exception Examples x
2.6.8.5.1. Default Multicycle Analysis 2.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.6.8.5.4. Same Frequency Clocks with Destination Clock Offset 2.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset Multicycle Constraint 2.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.7. Timing Analyzer Tcl Commands x
2.7.1. The quartus_sta Executable 2.7.2. Collection Commands
2.7.2. Collection Commands x
2.7.2.1. Wildcard Characters 2.7.2.2. Adding and Removing Collection Items 2.7.2.3. Query of Collections 2.7.2.4. Using the get_pins Command
1. Timing Analysis Introduction
2. Using the Intel® Quartus® Prime Timing Analyzer
A. Intel® Quartus® Prime Pro Edition User Guides

2.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset

This example is a combination of the previous two examples. The destination clock frequency is an integer multiple of the source clock frequency, and the destination clock has a positive phase shift. The destination clock frequency is 5 ns, and the source clock frequency is 10 ns. The destination clock also has a positive offset of 2 ns with respect to the source clock. The destination clock frequency can be an integer multiple of the source clock frequency. The destination clock frequency can be with an offset when a PLL generates both clocks with a phase shift on the destination clock.

The following example shows a design in which the destination clock frequency is a multiple of the source clock frequency with an offset.

Figure 135. Destination Clock is Multiple of Source Clock with Offset

The timing diagram for the default setup check analysis the Timing Analyzer performs.

Figure 136. Setup Timing Diagram
Figure 137. Setup Check Calculation

The setup relationship in this example demonstrates that the data does not require capture at edge one, but rather requires capture at edge three; therefore, you can relax the setup requirement. To adjust the default analysis, you shift the latch edge by two clock periods, and specify an end multicycle setup exception of three.

The multicycle exception adjusts the default analysis in this example:

Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
     -setup -end 3

The timing diagram for the preferred setup relationship for this example.

Figure 138. Preferred Setup Analysis

The following timing diagram shows the default hold check analysis that the Timing Analyzer performs with an end multicycle setup value of three:

Figure 139. Default Hold Check
Figure 140. Hold Check Calculation

In this example, the hold check one is too restrictive. The data is launched by the edge at 0 ns, and must check against the data that the previous latch edge at 2ns captures. You can use the multicycle hold assignment of 1 to correct this.

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