Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Using the Node Finder 1.3. Design Analysis & Elaboration 1.4. Design Synthesis 1.5. Design Place and Route 1.6. Incremental Optimization Flow 1.7. Fast Forward Compilation Flow 1.8. Full Compilation Flow 1.9. HSSI Dual Simplex IP Generation Flow 1.10. Exporting Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Synthesis Language Support 1.15. Synthesis Settings Reference 1.16. Fitter Settings Reference 1.17. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard 1.1.4. Design Netlist Infrastructure
1.1.4. Design Netlist Infrastructure x
1.1.4.1. DNI Netlist Five-Box Data Model
1.3. Design Analysis & Elaboration x
1.3.1. Using the RTL Analyzer 1.3.2. Use Case Examples
1.3.1. Using the RTL Analyzer x
1.3.1.1. Sweep Hints Viewer 1.3.1.2. Object Set Console 1.3.1.3. Module Interfaces 1.3.1.4. Bundled Instances 1.3.1.5. Auto-hide Unconnected Pins 1.3.1.6. Filtering Ports and Nets 1.3.1.7. Expand Connections
1.3.2. Use Case Examples x
1.3.2.1. Scripting Routine Tasks Using Tcl Commands 1.3.2.2. Traversing the Design Netlist Using Tcl Commands
1.4. Design Synthesis x
1.4.1. Preparing for Design Synthesis 1.4.2. Running Synthesis 1.4.3. Using Synopsys* Design Constraint (SDC) on RTL Files 1.4.4. Post-Synthesis Static Timing Analysis (STA) 1.4.5. Viewing Synthesis Reports 1.4.6. Viewing Synthesis Dynamic Report
1.4.2. Running Synthesis x
1.4.2.1. Preserving Registers During Synthesis 1.4.2.2. Preserving Signals for Monitoring and Debugging
1.4.3. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.4.3.1. Registering the SDC-on-RTL SDC File 1.4.3.2. Applying the SDC-on-RTL Constraints 1.4.3.3. Inspecting SDC-on-RTL Constraints 1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files 1.4.3.5. Using Entity-Based SDC-on-RTL Constraints 1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software 1.4.3.7. Example: Using SDC-on-RTL Features
1.5. Design Place and Route x
1.5.1. Running the Fitter 1.5.2. Viewing Fitter Reports
1.5.1. Running the Fitter x
1.5.1.1. Fitter Commands 1.5.1.2. Disabling or Enabling Physical Synthesis Optimization
1.5.2. Viewing Fitter Reports x
1.5.2.1. Plan Stage Reports 1.5.2.2. Place Stage Reports 1.5.2.3. Route Stage Reports 1.5.2.4. Retime Stage Reports 1.5.2.5. Finalize Stage Reports
1.5.2.2. Place Stage Reports x
1.5.2.2.1. Global Signal Visualization Report
1.5.2.3. Route Stage Reports x
1.5.2.3.1. Global Router Congestion Hotspot Summary Report 1.5.2.3.2. Global Router Wire Utilization Map Report
1.6. Incremental Optimization Flow x
1.6.1. Concurrent Analysis During Synthesis or Fitting 1.6.2. Analyzing Compiler Snapshots 1.6.3. Validating Periphery (I/O) after the Plan Stage
1.6.2. Analyzing Compiler Snapshots x
1.6.2.1. Running Snapshot Viewer
1.6.2.1. Running Snapshot Viewer x
1.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.6.2.1.2. Analyzing Clocking with Snapshot Viewer 1.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.6.2.1.5. Analyzing Congestion with Snapshot Viewer
1.7. Fast Forward Compilation Flow x
1.7.1. Step 1: Run Register Retiming 1.7.2. Step 2: Review Retiming Results 1.7.3. Step 3: Run Fast Forward Compile 1.7.4. Step 4: Review Fast Forward Results 1.7.5. Step 5: Implement Fast Forward Recommendations 1.7.6. Retiming Restrictions and Workarounds
1.7.2. Step 2: Review Retiming Results x
1.7.2.1. Locate Critical Chains
1.7.3. Step 3: Run Fast Forward Compile x
1.7.3.1. Fast Forward Compile By Hierarchy 1.7.3.2. HyperFlex Settings
1.7.4. Step 4: Review Fast Forward Results x
1.7.4.1. Clock Fmax Summary Report 1.7.4.2. Fast Forward Details Report
1.8. Full Compilation Flow x
1.8.1. Full Compilation Flow with Temporary Optimization Mode
1.10. Exporting Compilation Results x
1.10.1. Exporting a Version-Compatible Compilation Database 1.10.2. Importing a Version-Compatible Compilation Database 1.10.3. Creating a Design Partition 1.10.4. Exporting a Design Partition 1.10.5. Reusing a Design Partition 1.10.6. Viewing Quartus Database File Information 1.10.7. Clearing Compilation Results
1.10.6. Viewing Quartus Database File Information x
1.10.6.1. QDB File Attribute Types
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Precompiled Component (PCC) Generation Stage 1.12.3. Compilation on a Compute Farm 1.12.4. Allow Register Retiming 1.12.5. Automatic Gated Clock Conversion 1.12.6. Enable Intermediate Fitter Snapshots 1.12.7. Fast Preserve Option 1.12.8. Fractal Synthesis Optimization
1.12.8. Fractal Synthesis Optimization x
1.12.8.1. Enabling or Disabling Fractal Synthesis
1.14. Synthesis Language Support x
1.14.1. Verilog and SystemVerilog Synthesis Support 1.14.2. VHDL Synthesis Support
1.14.1. Verilog and SystemVerilog Synthesis Support x
1.14.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.14.1.2. Design Libraries 1.14.1.3. Verilog HDL Configuration 1.14.1.4. Initial Constructs and Memory System Tasks 1.14.1.5. Verilog HDL Macros
1.14.1.3. Verilog HDL Configuration x
1.14.1.3.1. Hierarchical Design Configurations
1.14.2. VHDL Synthesis Support x
1.14.2.1. VHDL Input Settings (Settings Dialog Box) 1.14.2.2. VHDL Standard Libraries and Packages 1.14.2.3. VHDL wait Constructs 1.14.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.15. Synthesis Settings Reference x
1.15.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Running the ECO Compilation Flow 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

2.2.2. Enabling Multi-Processor Compilation

The compiler can detect and use multiple processors to reduce total compilation time. By default, the compiler uses the setting specified under Parallel Compilation in the Processing page of the Options dialog box. To reserve some processors for other tasks, specify the maximum number of processors the software must use.

Using multiple processor cores provides several benefits for improving software performance as follows:

  • Faster execution: The Quartus® Prime software can support up to 24 processors, which means the software can run algorithms in parallel. This technique reduces the compilation time by up to 10% on systems with two processing cores and up to 20% on systems with four processors. When running timing analysis independently, two processors reduce the timing analysis time by an average of 10%. This reduction reaches an average of 15% when using four processors.
  • Increased throughput: With more processing cores, systems can execute multiple tasks simultaneously, which means the software can handle more requests simultaneously. The Quartus® Prime software may not necessarily utilize all the processors specified during compilation. The software has the flexibility to scale its usage to use up to the maximum number of processors specified. To achieve the highest possible throughput, Intel recommends using a system equipped with at least four processing cores, allowing the software to take full advantage of the available computing resources.
  • Reduced latency: With multiple processing cores, the software responds more quickly to your requests, improving the overall experience. The software never uses more than the specified number of processors, so you can work on other tasks in parallel without slowing down your computer.
  • More efficient resource utilization: By distributing tasks across multiple processor cores, the Quartus® Prime software can use available resources more efficiently, reducing the overall cost of running the software.

The use of multiple processors does not affect the quality of the fit. The fit is the same and deterministic for a given Fitter seed and given Maximum processors allowed setting on a specific design. This remains true regardless of the target system and the number of available processors. Different Maximum processors allowed specifications produces different results of the same quality. The impact is similar to changing the Fitter seed setting.

To enable multiprocessor compilation, follow these steps:

  1. Open or create an Quartus® Prime project.
  2. Click Assignments > Settings > Compilation Process Settings.
  3. Under Parallel compilation, specify options for the number of processors the compiler uses.

    View the number of processors detected on your system in the Parallel Compilation report after compilation ends.

    Figure 143. Parallel Compilation Report

    The following is the QSF setting that controls the maximum number of processors. If this line is in your project's QSF file, do not specify it again. 

    set_global_assignment -name NUM_PARALLEL_PROCESSORS <value>

    In this case, <value> is an integer from 1 to 24.

    If you want the Quartus® Prime software to detect the number of processors and use all the processors for the compilation, include the following Tcl command in your script: 

    set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
    Note:
    • Using multiple processor cores can help the Quartus® Prime software run faster, handle more tasks, and provide a better user experience. However, other factors, such as memory bandwidth or I/O bottlenecks, may limit performance. So, you must consider specific requirements and constraints of each project when deciding how many processor cores to use.
    • The compiler detects Intel® Hyper-Threading® Technology (Intel® HT Technology) as a single processor. If your system includes a single processor with Intel HT Technology, set the number of processors to one. Set the number of processors according to the number of physical processors in your system,

    The following are other factors that affect performance in the Quartus® Prime software:


Section Content
Processor Base Clock Frequency
Random Access Memory (RAM)
Storage

Level Two Title