Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Compiler Optimization Techniques 2.12. Synthesis Language Support 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Netlist Infrastructure x
2.3.1. DNI-Based Compilation Flow 2.3.2. DNI Netlist Five-Box Data Model 2.3.3. DNI-Based Node Finder 2.3.4. Exploring the RTL Analyzer 2.3.5. Early Timing Analysis After Design Synthesis 2.3.6. DNI Use Case Examples
2.3.4. Exploring the RTL Analyzer x
2.3.4.1. Sweep Hints Viewer 2.3.4.2. Object Set Console 2.3.4.3. Module Interfaces 2.3.4.4. Bundled Instances 2.3.4.5. Auto-hide Unconnected Pins 2.3.4.6. Filtering Ports and Nets 2.3.4.7. Expand Connections
2.3.5. Early Timing Analysis After Design Synthesis x
2.3.5.1. Synopsys* Design Constraint (SDC) on RTL 2.3.5.2. Post-Synthesis Static Timing Analysis (STA) 2.3.5.3. Types of SDC Files Used in the Intel® Quartus® Prime Software
2.3.5.1. Synopsys* Design Constraint (SDC) on RTL x
2.3.5.1.1. Registering the SDC-on-RTL SDC File 2.3.5.1.2. Applying the SDC-on-RTL Constraints 2.3.5.1.3. Inspecting SDC-on-RTL Constraints 2.3.5.1.4. Creating Constraints in SDC-on-RTL SDC Files 2.3.5.1.5. Using Entity-Based SDC-on-RTL Constraints
2.3.6. DNI Use Case Examples x
2.3.6.1. Scripting Routine Tasks Using DNI Tcl Commands 2.3.6.2. Traversing the DNI Netlist Using Tcl Commands 2.3.6.3. Using SDC-on-RTL Features
2.4. Design Synthesis x
2.4.1. Running Synthesis 2.4.2. Viewing Synthesis Reports 2.4.3. Viewing Synthesis Dynamic Report
2.4.1. Running Synthesis x
2.4.1.1. Preserving Registers During Synthesis 2.4.1.2. Preserving Signals for Monitoring and Debugging
2.5. Design Place and Route x
2.5.1. Running the Fitter 2.5.2. Viewing Fitter Reports
2.5.1. Running the Fitter x
2.5.1.1. Fitter Commands 2.5.1.2. Disabling or Enabling Physical Synthesis Optimization
2.5.2. Viewing Fitter Reports x
2.5.2.1. Plan Stage Reports 2.5.2.2. Place Stage Reports 2.5.2.3. Route Stage Reports 2.5.2.4. Retime Stage Reports 2.5.2.5. Finalize Stage Reports
2.5.2.2. Place Stage Reports x
2.5.2.2.1. Global Signal Visualization Report
2.5.2.3. Route Stage Reports x
2.5.2.3.1. Global Router Congestion Hotspot Summary Report 2.5.2.3.2. Global Router Wire Utilization Map Report
2.6. Incremental Optimization Flow x
2.6.1. Concurrent Analysis During Synthesis or Fitting 2.6.2. Analyzing Compiler Snapshots 2.6.3. Validating Periphery (I/O) after the Plan Stage
2.6.2. Analyzing Compiler Snapshots x
2.6.2.1. Running Snapshot Viewer
2.6.2.1. Running Snapshot Viewer x
2.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.6.2.1.2. Analyzing Clocking with Snapshot Viewer 2.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.6.2.1.5. Analyzing Congestion with Snapshot Viewer
2.7. Fast Forward Compilation Flow x
2.7.1. Step 1: Run Register Retiming 2.7.2. Step 2: Review Retiming Results 2.7.3. Step 3: Run Fast Forward Compile 2.7.4. Step 4: Review Fast Forward Results 2.7.5. Step 5: Implement Fast Forward Recommendations 2.7.6. Retiming Restrictions and Workarounds
2.7.2. Step 2: Review Retiming Results x
2.7.2.1. Locate Critical Chains
2.7.3. Step 3: Run Fast Forward Compile x
2.7.3.1. Fast Forward Compile By Hierarchy 2.7.3.2. HyperFlex Settings
2.7.4. Step 4: Review Fast Forward Results x
2.7.4.1. Clock Fmax Summary Report 2.7.4.2. Fast Forward Details Report
2.8. Full Compilation Flow x
2.8.1. Full Compilation Flow with Temporary Optimization Mode
2.9. Exporting Compilation Results x
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
2.9.6. Viewing Quartus Database File Information x
2.9.6.1. QDB File Attribute Types
2.10. Integrating Other EDA Tools x
2.10.1. Generating a VQM Netlist for other EDA Tools
2.11. Compiler Optimization Techniques x
2.11.1. Compiler Optimization Modes 2.11.2. Allow Register Retiming 2.11.3. Automatic Gated Clock Conversion 2.11.4. Enable Intermediate Fitter Snapshots 2.11.5. Fast Preserve Option 2.11.6. Fractal Synthesis Optimization
2.11.6. Fractal Synthesis Optimization x
2.11.6.1. Enabling or Disabling Fractal Synthesis
2.12. Synthesis Language Support x
2.12.1. Verilog and SystemVerilog Synthesis Support 2.12.2. VHDL Synthesis Support
2.12.1. Verilog and SystemVerilog Synthesis Support x
2.12.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.12.1.2. Design Libraries 2.12.1.3. Verilog HDL Configuration 2.12.1.4. Initial Constructs and Memory System Tasks 2.12.1.5. Verilog HDL Macros
2.12.1.3. Verilog HDL Configuration x
2.12.1.3.1. Hierarchical Design Configurations
2.12.2. VHDL Synthesis Support x
2.12.2.1. VHDL Input Settings (Settings Dialog Box) 2.12.2.2. VHDL Standard Libraries and Packages 2.12.2.3. VHDL wait Constructs 2.12.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.13. Synthesis Settings Reference x
2.13.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.2.2. Enabling Multi-Processor Compilation x
3.2.2.1. Processor Base Clock Frequency 3.2.2.2. Random Access Memory (RAM) 3.2.2.3. Storage
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

3.5.1. Identifying Routing Congestion with the Chip Planner

To identify areas of routing congestion in your design:
  1. Click Tools > Chip Planner.
  2. To view the routing congestion in the Chip Planner, double-click the Report Routing Utilization command in the Tasks list.
  3. Click Preview in the Report Routing Utilization dialog box to preview the default congestion display.
  4. Change the Routing utilization type to display congestion for specific resources. The default display uses dark blue for 0% congestion and red for 100%.
  5. Adjust the slider for Threshold percentage to change the congestion threshold level.
The Intel® Quartus® Prime compilation messages contain information about average and peak interconnect usage. Peak interconnect usage over 75%, or average interconnect usage over 60% indicate possible difficulties fitting your design. Similarly, peak interconnect usage over 90%, or average interconnect usage over 75%, indicate a high chance of not getting a valid fit.

Section Content
Areas with Routing Congestion
Congestion due to HDL Coding style

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