Triple-Speed Ethernet Intel® FPGA IP Release Notes

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ID 683215
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0 1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 2.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 2.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 2.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 2.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 2.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 2.9. Triple-Speed Ethernet Intel® FPGA IP v19.1 2.10. Triple-Speed Ethernet Intel® FPGA IP v18.0 2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.12. Triple Speed Ethernet IP Core v15.1 2.13. Triple Speed Ethernet IP Core v15.0 2.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.15. Triple Speed Ethernet IP Core v14.0 2.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.17. Triple Speed Ethernet IP Core v13.1 2.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 2.19. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes

2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0

Table 6.  v21.2.0 2023.04.03
Quartus® Prime Version Description Impact
23.1
  • Added IEEE 1588v2 Precision Time Protocol (PTP) support for 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS with transceiver variant operating without internal FIFO buffer in full-duplex mode on Agilex™ 7 F-tile devices.
  • SYSPLL is available for datapath clocking when Enable F-tile Transceiver Dynamic Reconfiguration (SYSPLL MODE) is turned on for MAC with 2xTBI and Embedded PMA TSE IP variant on Agilex™ 7 F-tile devices.
  • Enable Datapath Avalon Interface & Enable PMA Avalon Interface are available for both PMA and SYSPLL data path clocking mode for MAC with 2XTBI and Embedded PMA TSE IP Variant on Agilex™ 7 F-tile devices.
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MAC RX accepts 6-bytes and 7-bytes preamble frames.
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