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2.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0
2.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0
2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0
2.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0
2.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0
2.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0
2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0
2.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0
2.9. Triple-Speed Ethernet Intel® FPGA IP v19.1
2.10. Triple-Speed Ethernet Intel® FPGA IP v18.0
2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1
2.12. Triple Speed Ethernet IP Core v15.1
2.13. Triple Speed Ethernet IP Core v15.0
2.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition
2.15. Triple Speed Ethernet IP Core v14.0
2.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition
2.17. Triple Speed Ethernet IP Core v13.1
2.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
2.19. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
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2.13. Triple Speed Ethernet IP Core v15.0
| Description | Impact |
|---|---|
| You may observe hold time violation in designs targeting the Stratix® V, Arria® V, Cyclone® V, and Arria® 10 (10AS066ES) devices in this release. | Refer to the following errata for more information and the workaround: Hold Time Violation in Triple Speed Ethernet IP Core. |