Visible to Intel only — GUID: vmi1660552183702
Ixiasoft
2.1. Triple-Speed Ethernet (altera_eth_tse) Intel® FPGA IP v22.4.0
2.2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) v22.3.0
2.3. Triple-Speed Ethernet (altera_eth_tse) v22.2.0
2.4. Triple-Speed Ethernet Intel® FPGA IP v22.1.0
2.5. Triple-Speed Ethernet Intel® FPGA IP v22.0.0
2.6. Triple-Speed Ethernet Intel® FPGA IP v21.2.0
2.7. Triple-Speed Ethernet Intel® FPGA IP v21.1.0
2.8. Triple-Speed Ethernet Intel® FPGA IP v20.0.0
2.9. Triple-Speed Ethernet Intel® FPGA IP v19.5.0
2.10. Triple-Speed Ethernet Intel® FPGA IP v19.4.0
2.11. Triple-Speed Ethernet Intel® FPGA IP v19.2.0
2.12. Triple-Speed Ethernet Intel® FPGA IP v19.1
2.13. Triple-Speed Ethernet Intel® FPGA IP v18.0
2.14. Intel FPGA Triple Speed Ethernet IP Core v17.1
2.15. Triple Speed Ethernet IP Core v15.1
2.16. Triple Speed Ethernet IP Core v15.0
2.17. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition
2.18. Triple Speed Ethernet IP Core v14.0
2.19. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition
2.20. Triple Speed Ethernet IP Core v13.1
2.21. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
2.22. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
Visible to Intel only — GUID: vmi1660552183702
Ixiasoft
2.7. Triple-Speed Ethernet Intel® FPGA IP v21.1.0
Quartus® Prime Version | Description | Impact |
---|---|---|
22.4 | Added 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS variant for Intel Stratix 10 devices. | — |
MAC RX accepts 7-bytes preamble frames only. |
Quartus® Prime Version | Description | Impact |
---|---|---|
22.3 | Added the following design example for Agilex™ 7 devices
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