Triple-Speed Ethernet Intel® FPGA IP Release Notes

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ID 683215
Date 7/08/2024
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1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0 1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 2.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 2.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 2.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 2.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 2.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 2.9. Triple-Speed Ethernet Intel® FPGA IP v19.1 2.10. Triple-Speed Ethernet Intel® FPGA IP v18.0 2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.12. Triple Speed Ethernet IP Core v15.1 2.13. Triple Speed Ethernet IP Core v15.0 2.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.15. Triple Speed Ethernet IP Core v14.0 2.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.17. Triple Speed Ethernet IP Core v13.1 2.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 2.19. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes

2.17. Triple Speed Ethernet IP Core v13.1

Table 24.  v13.1 November 2013
Description Impact
Removed support for the following devices:
  • Arria GX
  • Cyclone II
  • HardCopy II, HardCopy III, and HardCopy IV
  • Stratix II and Stratix II GX
-
Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V devices. -
Added 1588v2 support for MAC-only variants -
Added ATX and CMU Tx PLL options for variations that include the PCS block targeting Arria V GZ and Stratix V devices. -
Added SyncE support by separating Tx PLL and Rx PLL reference clock. -
The period in nanosecond for csr registers: tx_period, rx_period, Period, and AdjustPeriod, was changed from bit 16 to 19 to bit 16 to 24. -
Level Two Title