Triple-Speed Ethernet Intel® FPGA IP Release Notes

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ID 683215
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0 1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 2.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 2.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 2.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 2.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 2.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 2.9. Triple-Speed Ethernet Intel® FPGA IP v19.1 2.10. Triple-Speed Ethernet Intel® FPGA IP v18.0 2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.12. Triple Speed Ethernet IP Core v15.1 2.13. Triple Speed Ethernet IP Core v15.0 2.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.15. Triple Speed Ethernet IP Core v14.0 2.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.17. Triple Speed Ethernet IP Core v13.1 2.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 2.19. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes

2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0

Table 11.  v19.4.0 2021.06.23
Quartus® Prime Version Description Impact
21.2

Added deterministic latency support for 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and IEEE 1588v2 feature enabled variation operating without internal FIFO buffer in full-duplex mode.

This feature is only supported in the Stratix® 10 E-tile devices.

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Design Example for Triple-Speed Ethernet Intel® FPGA IP:
  • Added the following design example for Stratix® 10 E-tile devices:
    • 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
 —
Table 12.  v19.4.0 2021.04.01
Quartus® Prime Version Description Impact
21.1 Design Example for Triple-Speed Ethernet Intel® FPGA IP:
  • Added the following design example for Stratix® 10 E-tile devices:
    • 10/100/1000 Mb Ethernet MAC (Fifoless) with 1000 BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
 —
Table 13.  v19.4.0 2020.12.14
Quartus® Prime Version Description Impact
20.4 Added support for two new core variants for Stratix® 10 E-tile devices:
  • 10/100/1000-Mbps Ethernet MAC without internal FIFO buffers with 1000BASE-X/SGMII 2XTBI PCS
  • 10/100/1000-Mbps Ethernet MAC without internal FIFO buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS
 —
Table 14.  v19.4.0 2019.12.16
Quartus® Prime Version Description Impact
19.4 Added support for the Agilex™ 7 device family. —
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